The present invention relates to a dynamic RAM structure in which a memory cell comprises one MOS transistor and one capacitor and the manufacturing method thereof.
Recently, an integration of the dynamic RAM (DRAM) is rapidly advanced. In order that the DRAM may have a further higher integration, such various cells as a so-called stack-type cell in which the capacitors are stacked on the transistor, a so-called trench-type cell in which a trench is formed in a silicon substrate in such a manner that an inner wall of the trench is used as the capacitor and the like are proposed as a memory cell structure. More specifically, in case of the trench-type cell, the deeper a depth of the trench becomes, the more a storage capacitance (Cs) can be increased. Accordingly, the trench-type cell is considered as such a memory cell structure that a large storage capacitance can be realized even if the memory cell has less area.
Furthermore, in the trench-type cell, as means for electrically connecting one electrode of the capacitor in the trench to a source/drain diffusion layer of a selecting MOS transistor, there are a surface strap scheme in which a surface strap is disposed on a substrate surface for connecting, and a buried strap scheme (BS scheme) in which a side-wall contact is formed on a side wall of the upper portion of the trench. Instead of the surface strap scheme, the trench-type cell of the BS scheme is applied to the DRAM of 256M-bit generation. The surface strap (SS) scheme needs an additional cell area to connect one electrode of the capacitor to a source/drain diffusion layer of the MOS transistor. Therefore buried strap scheme (BS scheme) is better than SS scheme in the cell area scaling point of view.
However, in the trench-type cell of the BS scheme, it is not easy to control the depth of the side-wall contact along the upper portion of the trench, and it is difficult to reduce a distance between a gate conductor (GC) of the MOS transistor and a deep trench (DT). The depth from the side-wall contact is not so large, around 0.1 .mu.m. However, the depth from the Si surface is large, around 0.20 .mu.m. In the case of alignment error between DT and GC, this deeper diffusion layer works as a source/drain diffusion layer with a deeper Xj (Junction depth). Therefore, there is such a problem that it is difficult to reduce the cell area for a next generation.
For example, such a typical trench-type cell that a trench capacitor's storage node electrode is to the source/drain of the MOS transistor by using the BS scheme is disclosed in Technical Digest Paper, pp. 627 to 630, IEDM, 1993. Although this design of the cell is very excellent in 0.25 .mu.m-rule generation, since a side-wall diffusion area is formed on the side-wall of the upper portion of the trench at a depth of approximately 0.2 .mu.m from the Si surface, it is difficult to reduce the distance between the gate conductor (GC) of the MOS transistor and a deep trench capacitor. That is, when the side-wall diffusion area approaches the gate conductor of the MOS transistor, the side-wall diffusion area becomes the source/drain itself of the MOS transistor, whereby shapes of the source and drain become asymmetrical. Accordingly there is such a problem that a punch-through occurs. Moreover, this asymmetrical shape is not preferable for further scaling of the gate length of the MOS transistor. Furthermore, such a BS scheme is needed to precisely control the depth of the buried strap and a surface condition (cleanness) in a side-wall area. So as to take a stable contact, it is necessary to clean the side-wall area. Moreover, since the side-wall area is required to be deeper, it is necessary to form a deeper Shallow Trench Isolation (STI) in order to cut the diffusion area off from the side-wall. However, since in order that the deeper STI is formed, it is necessary to bury a deeper STI area with high aspect ratio by using an SiO.sub.2 film, it is difficult to manufacture the dynamic RAM structure.
In "Symposium on VLSI Technology Digest of Technical Paper, p. p. 137 to 138, 1995", such a technique is disclosed wherein an SEG (selective-epitaxial growth) technique is used so as to form an SEG layer on an active area and a storage node of a trench capacitor thereby one part of the SEG layer is used as a strap electrode.
However, in the technique, a field isolation layer is formed prior to forming the SEG layer. The field isolation layer is formed before forming the SEG layer, so that a polysilicon layer grows on the field isolation layer during the SEG. An Si layer having less crystallizability results in one part of the channel along the field isolation layer in a longitudinal direction of the channel of the MOS transistor and the channel region. There is the problem that a leakage current is increased between the source and the drain of the MOS transistor through these polysilicon layers.